1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device configured to perform a write operation in such an improved manner that when data is copied from sequential storage area within a storage device as a copy source coupled to the memory device from the outside of the memory device to sequential storage area within a non-volatile semiconductor storage means as a copy destination within the memory device.
2. Description of Related Art
With the recent progress in microfabrication techniques, miniaturization of semiconductor elements has been enhanced and accordingly, an LSI consisting of the semiconductor elements has been becoming larger in size, and particularly, an LSI semiconductor memory has extensively, been becoming larger.
For instance, a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM) as a semiconductor memory having a storage capacity of 256 mega-bits in one chip has become commercially available. Although the aforementioned memories are a volatile semiconductor memory device, a variety of devices such as a read only memory (ROM) used to only read data thereform, an EEPROM and a flash memory, both allowing electrical re-write of data, can be used as a non-volatile memory device and all those memories have been developed to have larger storage capacity. In this case, a flash memory refers to a flash EEPROM as an EEPROM capable of electrically erasing at one time data within each block or at one time data corresponding to all bits.
Since the flash memory is advantageously able to have larger storage capacity, the flash memory is not limited in its application to a conventional EEPROM (UV-EPROM) for storage of a program for controlling a computer system or an electronic equipment but has widely been used, utilizing its large storage capacity, such as in a digital still camera or a mobile equipment.
Furthermore, in an EEPROM, erase and write operations are performed in unit of 1 byte. In contrast, in a flash memory, an erase operation is performed in unit of block and further a write operation is performed in unit of 1 byte. A flash memory writes data about 1000 times faster than an EEPROM does and is suitably used in data storage application such as a disk, utilizing its ability to write data at high speed.
When a write operation or an erase operation is performed on a flash memory, a control command such as a write command or an erase command is supplied to the flash memory and then the flash memory performs operation following the command.
In general, one functional operation is performed in two cycles, i. e., a cycle for inputting a command code used in an operation mode and a cycle for inputting the contents of data.
A conventional write operation of this type performed on a flash memory and associated with the invention is constructed such that data is automatically written to an associated memory cell inside the memory and then verification is made to verify whether the data is written. In this case, since a time interval required for writing the data to the memory cell is not constant, the time when the write operation has completed is not constant accordingly.
Referring to FIG. 13 illustrating a timing chart to explain a write operation performed on the conventional flash memory, data indicative of an auto write command is represented by, for example, 4 cycles, AAh, 55h, A0h and PD. Though not shown herein, addresses corresponding to those cycles are assumed to be 555, 2AA, 555 and PA. Note that PD denotes program data and PA denotes a program address.
A read operation is performed when a Ready/Busy# signal indicative of operating status of the flash memory is being at a logical high level (Ready) and a write operation is performed when the signal is being at a logical low level (Busy#). In this case, when the number of write operations reaches a specific limitation value, additional number of write operations need to be limited to a small value even if the data stored in a memory cell and the program data PD do not coincide with each other. The write duration ranges from about 11 microseconds to about 200 microseconds and is not constant.
For this reason, when write operations are performed on sequential addresses, whether the write operation has completed is verified outside the memory and upon verification of completion of the operation, a write operation is performed on the subsequent address. This imposes burden on the verification of completion, the write command and further a control circuit.
Furthermore, recently, a multi-chip package has become commercially available and then a flash memory chip and an SRAM chip have been incorporated together in one package, increasing the need for write function provided by the invention.
An example of the conventional flash memory, associated with the invention, of this type is disclosed in Japanese Patent Application 2001-6379. Referring to FIG. 14 illustrating the configuration of the flash memory disclosed in the publication, the flash memory comprises: 4 cell blocks CBL0 to CBL3; an address buffer 910 for receiving addresses A0 to A19; and address latch circuits 911 for latching addresses A0 to A19 via the address buffer 910. The address latch circuits 911 are provided to correspond to the individual cell blocks and to latch addresses corresponding to the individual cell blocks.
The flash memory further includes: a command input circuit 912 for receiving a specific control signal CNT and a command signal supplied via the address buffer 910 and a data input/output buffer 916; and a control circuit 913 to which the received command signal of predetermined bits is supplied.
The control circuit 913 controls internal circuits so that the internal circuits perform a later described copy operation and move and integration operations in addition to write (program), erase and read operations that are performed in the conventional flash memory. The remaining configuration of the flash memory is omitted herein for convenience.
In the conventional flash memory, for example, in case of copy operation, a data copy command is input to the command input circuit 912. Then, the address of a cell block from which data is to be copied (hereinafter, a memory location from which data is to be copied is referred to as a copy source) is input to the circuit 912.
Subsequently, the data copy command is supplied to the control circuit 913 and then the address of a cell block as a copy source is supplied to the circuit 913. The address of a cell block to which data is to be copied (hereinafter, a memory location to which data is to be copied is referred to as a copy destination) is latched in the address latch circuit 911.
Data stored in the cell block as a copy destination is sequentially read by a sequence program within the control circuit 913 and is inspected whether bits indicative of data within the cell block are all in an erased state (data “1”). When the bits are not all in an erased state, the data stored in the corresponding cell block is erased following the conventional erase operation.
Upon completion of the erasing of the individual data bits stored in the cell block as a copy destination, the data stored in the cell block as a copy source is read. The read data is latched in a data latch circuit 915 and the read data being latched therein is written to the cell block as a copy destination.
A data read operation is repeatedly performed on the cell block as a copy source until the read operation is performed on all bits within the cell block, and a write operation is repeatedly performed on the cell block as a copy destination until the write operation is performed on all bits within the cell block.
The copy operation is comprised of verification of the erased state of a cell block as a copy destination, incrementation of addresses within cell blocks as a copy source and a copy destination, and control of incrementation of addresses within a cell block as a copy destination, and the remainder of the copy operation is realized by the combination of the conventional read, erase, write operations.
As described above, a write operation is performed on the conventional non-volatile semiconductor memory so that data is automatically written inside the memory and a verification operation is performed to verify the written data. However, since a time interval required to write data to a memory cell is not constant, the time when the write operation has completed is undesirably not constant.
Furthermore, when a write operation is performed on sequential addresses, completion of the write operation is verified outside the memory and upon verification of completion of the operation, the subsequent write operation is performed on the subsequent address, undesirably imposing burden on the verification of completion of the operation, the write command and further the control circuit.
Moreover, since the exemplary memory disclosed in Japanese Patent Application 2001-6379 does not have means for allocating an area to which data is written, the address latch circuits 911 need to be provided corresponding to individual cell blocks, increasing the number of components constituting the memory and the size of chip incorporating therein the memory.